High-speed memory circuits require the generation of internal clocks that are initiated by the transition of an external address in order to deselect and select memory cells, equalize critical nodes and initiate sensing of addressed data. The access time of a memory circuit is, therefore, a direct function of the delay incurred in detecting an address transition and generating the internal clock, referred to below as an Address Transition Detection (ATD) pulse. An ATD pulse is generated by each of the individual address inputs to the memory; the individual pulses are then summed to generate a global ATD signal.
High-speed memories are often segmented into blocks of rows and columns of storage cells in order to improve access speed and reduce power dissipation. As a result of this segmented architecture, the ATD pulse requirements for address changes within a currently addressed memory block versus address changes that result in memory cell selections outside the currently addressed memory block are different. The ATD concepts utilized in the present invention optimize the internal clock global ATD signal based on whether a specific address change is an intra- or an inter-block change. This will be referred to below as an "hierarchical" ATD scheme.
FIG. 1 shows a conventional address buffer and ATD circuit 10 that utilizes a pair of delay chains 11 and 12 to feed a NOR gate network 13. The NOR gate network 13 provides an output which, after propagation through an intermediate summing NOR circuit, i.e., NOR gate 14 and buffer inverter 15 in FIG. 1, serves as an address transition detection pulse ATDx.
As shown in FIG. 1A, each of the n address buffers in the memory circuit generates its own address transition detection pulse ATDx which serves as an input to a corresponding n-channel pull-down transistor Qx in a summing circuit 20. The output of the summing circuit 20 is buffered by an inverter 21 to generate the global output signal "ATDglobal". Each address transition detection pulse ATDx pulls down node "ATDlocal" which is then returned to a logic high by a p-channel load transistor 22 upon the termination of the ATDx pulse. Thus, overlapping ATDx signals from the n address buffers 10 in the memory circuit are summed by the summing circuit 20 to generate the composite ATDglobal signal.